All-Digital Phase Locked Loop (ADPLL)
My strong commitment to research projects stemmed from my belief that an undergraduate education ought to go beyond theory and delve into practice. While theory is an indispensable part of an engineering program, practical experience is necessary to gain a comprehensive understanding of the basis and application of theory. Even as electrical products have shrunk over the last decade, the integrated circuit remains the key component. Therefore, during my time at NTU, I first volunteered to work on a project concerning a digital phase lock loop in a microelectronic circuits class taught by Prof. Shen-Iuan Liu in my sophomore year. With this project, we attempted to make the traditional analog phase lock loop into an all-digital field. By understanding the function of each block and deriving a mathematical model, we came up with the parameters of ADPLL, such as KP and KI gain, LPF bit number, DCO resolution, and DSM frequency, and used Matlab Simulink to verify behavior simulation. For the analog circuit, we used Synopsys HSpice to model and inspect the waveforms via Synopsys Custom WaveView and Cosmos scope. For digital simulation, we wrote Verilog to qualified specifications with ModelSim and Co-simulated with Matlab. After verification, we applied HSpice to do a closed-loop simulation to substantiate the entire system by changing Verilog to Verilog-A and combined it with analog circuit. We used co-simulated Verilog to finish Gate Level synthesis via the Synopsys Design compiler. With an eye to finishing the digital circuit layout, we employed Cadence SOC Encounter to do Place and Route. Setting up an analog circuit with Synopsys Laker ADP, we used PAR to combine the digital and analog circuits. Before tape-out, we leveraged Calibre to verify DRC and LVS and run a post-layout simulation.